library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity sl2 is
    port(
    a: in std_logic_vector(31 downto 0);
    y: out std_logic_vector(31 downto 0)
    );
end sl2;

architecture behav of sl2 is
begin
    y <= shl(a, conv_std_logic_vector(2, 32));
end behav;
